1 memory all data sheets are subjec t to change without notice (858) 503-3300- fax: (858) 503-3301- www.maxwell.com 14-bit, 10 msps monolithic a/d 9240lp ?2002 maxwell technologies all rights reserved. converter with lpt asic 03.08.02 rev 4 f eatures : ?r ad -p ak ? radiation-hardened against natural space radia- tion ? low power dissipation: 230 mw ? single 5 v supply ? integral nonlinearity error: 2.5 lsb ? differential nonlinearity error: 0.6 lsb ? input referred noise: 0.36 lsb ? complete: on-chip sample-and-hold amplifier and voltage reference ? signal-to-noise ratio: 77 db ? spurious-free dynamic range: 90 db ? out-of-range indicator ? straight binary output data ? total dose hardened to 100 krads (si), dependent on orbit and mission duration ? single event latchup (sel) protected d escription : maxwell technologies? 9240lp is a 14-bit, analog-to-digital converter that operates at a 10 msps rate. manufactured with a high speed cmos process, this monolithic adc contains an on-chip, high performance, low noise, sample-and-hold ampli- fier and programmable voltage reference. the 9240lp offers single supply operation and dissipates only 230mw with a 5 volt supply. this device provides no missing codes and excellent temperatur e drift performance over the full operating temperature range. the 9240lp utilizes maxwell?s lpt? latchup protection cir- cuit. maxwell technologies' patented r ad -p ak ? packaging technol- ogy incorporates radiation shie lding in the microcircuit pack- age. it eliminates the need for box shielding while providing the required radiation shielding fo r a lifetime in orbit or space mission. in a geo orbit, r ad -p ak provides protection to 100 krad (si) radiation dose toleranc e. this product is available with screening up to class s.
memory 2 all data sheets are subjec t to change without notice ?2002 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/ d converter with lpt asic 9240lp 03.08.02 rev 4 t able 1. 9240lp p in d escription p in n umber n ame d escription 1 dvss digital ground 2, 29 avss analog ground 3 dvdd 5v digital supply 4, 28 avdd 5v analog supply 5 nc no connect 6 drvdd digital output driver supply 7 clk clock input pin 8 lptstatus a 0 to 5v pulse is output during the decision time and protect time. normally low. 9 lptbit the lpt circuit will crowbar the power supplies to the 9240lp for as long as a logic high is applied. used to verify operation of the lpt. normally a logical low or ground is applied to this input. 10 nc no connect 11 bit 14 least significant data bit (lsb) 12-23 bit 13-bit 2 data output bits 24 bit 1 most significant data bits (msb) 25 otr out of range 26, 27, 30 nc no connect 31 sense reference select 32 v ref reference i/o 33 refcom reference common 34, 38 nc no connect 35 bias power/speed programming 36 capb noise reduction pin 37 capt noise reduction pin 39 cml common-mod level (midsupply) 40 lptv ref protected reference i/o 41 v in a analog input pin (+) 42 v in b analog input pin (-) 43 lptdvdd protected 5v digital supply 44 lptavdd protected 5v analog supply
memory 3 all data sheets are subjec t to change without notice ?2002 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/ d converter with lpt asic 9240lp 03.08.02 rev 4 t able 2. 9240lp a bsolute m aximum r atings 1 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the dev ice at these or any other conditions abov e those indicated in the operational sec- tions of this specification are not imp lied. exposure to absolute maximum ratings for extended periods may effect device reli- ability. p arameter s ymbol w ith r espect t o m in m ax u nit +5 v analog supply avdd avss -0.3 6.5 v +5 v digital supply dvdd dvss -0.3 6.5 v analog ground avss dvss -0.3 0.3 v +5 v analog supply avdd dvdd -6.5 6.5 v digital output driver supply drvdd drvss -0.3 6.5 v digital output driver ground drvss avss -0.3 0.3 v reference common refcom avss -0.3 0.3 v clock input pin clk avss -0.3 avdd v digital outputs data out bits drvss -0.3 dvdd v analog inputs v in a, v in b avss -0.3 avdd v reference i/o v ref avss -0.3 avdd v reference select sense avss -0.3 avdd v noise reduction pins capb, capt avss -0.3 avdd v power/speed programming bias avss -0.3 avdd - 0.6 v junction temperature t j -- 150 c operating temperature t a -55 125 c storage temperature t stg -65 150 c lead temperature (10 sec) t l -- 300 c t able 3. d elta l imits p arameter v ariation i cc 10% of specified value in t able 4
memory 4 all data sheets are subjec t to change without notice ?2002 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/ d converter with lpt asic 9240lp 03.08.02 rev 4 t able 4. 9240lp dc s pecifications (avdd = 5v, dvdd = 5v, drvdd = 5v, r bias = 2 k ? , v ref = 2.5v,v in a = v in b = 2.5v d ifferential i nput c entered on v ref (1.25v to 3.75v a bsolute ), t a = -55 to +125c, unless otherwise specified ) p arameter s ubgroups m in t yp 1 m ax u nit resolution 1 14 -- -- bits max referred noise 1 v ref = 1 v v ref = 2.5v -- -- 0.9 0.36 -- -- lsb rms lsb rms accuracy 2 integral nonlinearity (inl) differential nonlinearity (dnl) inl 3 dnl 3 no missing codes zero error (@ 25 c) gain error (@ 25 c) 4,1 gain error (@ 25 c) 5 1, 2, 3 1, 2, 3 1, 2, 3 1 1 -- 1 -3.0 -- -- -- -- .3 1.5 0.75 2.5 0.6 2.5 0.7 -- -- -- +3.0 1.0 -- -- 14 +.3 1.5 0.75 lsb lsb lsb lsb bits guaranteed % fsr % fsr % fsr temperature drift zero error gain error 4 gain error 5 1, 2, 3 -- -- -- 3.0 20.0 5.0 -- -- -- ppm/c ppm/c ppm/c power supply rejection 1, 2, 3 -- -- 0.1 % fsr analog input 1 input span (with v ref = 1.0 v) 1 (with v ref = 2.5 v) input (v in a or v in b) range input capacitance 1 1, 2, 3 -- 2 -- 0 -- -- -- -- 16 -- 5 avdd -.25 v p-p v p-p v pf internal voltage reference 1 output voltage (1v mode) output voltage tolerance (1 v mode) output voltage (2.5 v mode) output voltage tolerance (2.5 v mode) load regulation v ref 6 load regulation lptv ref 1, 6, 7 -- -- -- -- -- -- -- 1 -- 2.5 -- 10 -- -- 14 -- 35 -- 10.0 volts mv volts mv mv mv reference input resistance 1, 2, 3 -- 5 -- k ?
memory 5 all data sheets are subjec t to change without notice ?2002 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/ d converter with lpt asic 9240lp 03.08.02 rev 4 lpt asic rds on - v ref - v in a - v in b latchup protection - decision time - protect time - avdd trip current - avdd trip current tolerance - dvdd trip current - dvdd trip current tolerance 1, 2, 3 -- -- -- -- -- -- -- -- -- 8 8 105 105 10 70 75 15 28 5 15 -- -- -- -- -- -- -- -- -- ohm ohm ohm ohm s s ma ma ma ma power supplies supply voltages - avdd - dvdd - drvdd supply current - iavdd - idvdd 1, 2, 3 1, 2, 3 -- -- -- -- -- 5 5 5 43 3 -- -- -- 55 16 v (5% avdd operating) v (5% dvdd operating) v (5% drvdd operating) ma ma power consumption 8 1, 2, 3 230 355 mw 1. guaranteed by design. 2. tested using external v ref with servo control 3. v ref = 1v 4. including internal reference. 5. excluding internal reference. 6. load regulation with 1 ma load current. 7. lptv ref should not be capacitively loaded above 0.1 f. 8. calculated from i dd t able 4. 9240lp dc s pecifications (avdd = 5v, dvdd = 5v, drvdd = 5v, r bias = 2 k ? , v ref = 2.5v,v in a = v in b = 2.5v d ifferential i nput c entered on v ref (1.25v to 3.75v a bsolute ), t a = -55 to +125c, unless otherwise specified ) p arameter s ubgroups m in t yp 1 m ax u nit
memory 6 all data sheets are subjec t to change without notice ?2002 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/ d converter with lpt asic 9240lp 03.08.02 rev 4 t able 5. 9240lp ac s pecifications (avdd = 5v, dvdd = 5v, drvdd = 5v, f sample = 10 msps, r bias = 2 k ? , v ref = 2.5v, a in = -0.5 dbfs, ac c oupled /d ifferential i nput , t a = -55 to +125c, unless otherwise specified ) p arameter s ubgroups m in t yp m ax u nit signal-to-noise and distortion ratio (s/n+d) f input = 500 khz f input = 1.0 mhz f input = 5.0 mhz -- -- -- 76.0 76 74.5 -- -- -- db db db db effective number of bits (enob) 1 f input = 500 khz f input = 1.0 mhz f input = 5.0 mhz 1. enob calculated from snr. 12 -- -- -- -- 12.5 12.3 11.9 -- -- -- -- bits bits bits bits signal-to-noise ratio (snr) f input = 500 khz f input = 1.0 mhz f input = 5.0 mhz 4, 5, 6 74.5 -- -- -- 77 77 77 77 -- -- -- -- db db db db total harmonic distortion (thd) f input = 500 khz f input = 1.0 mhz f input = 5.0 mhz -- -- -- -83 -83.0 -75.0 -- -- -- db db db spurious free dynamic range f input = 500 khz f input = 1.0 mhz f input = 5.0 mhz 4, 5, 6 -- -- -- 90.0 90.0 80.0 -- -- -- db db db dynamic performance 2 full power bandwidth small signal bandwidth aperture delay aperture jitter acquisition to full-scale step (0.0025%) overvoltage recovery time 2. guaranteed by design. -- -- -- -- -- -- 70 70 1 4 45 167 -- -- -- -- -- -- mhz mhz ns ps rms ns ns max conversion rate 9, 10, 11 10 -- -- mbits
memory 7 all data sheets are subjec t to change without notice ?2002 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/ d converter with lpt asic 9240lp 03.08.02 rev 4 t able 6. 9240lp d igital s pecifications (avdd = 5v, dvdd = 5v, t a = -55 to +125c, unless otherwise specified ) p arameter s ymbol s ubgroups m in t yp m ax u nit clock input high level input voltage 1 low level input voltage 1 high level input current (v in = dvdd) low level input current (v in = 0v) input capacitance 1. guaranteed by design. v ih v il i ih i il c in 1, 2, 3 -- -- -- -- -- -- -- -- -- 5 3.5 1.0 10 10 -- v v a a pf logic outputs (with drvdd = 5v) high level output voltage (i oh = 50 a) high level output voltage (i oh = 0.5 ma) low level output voltage (i ol = 1.6 ma) low level output voltage (i ol = 50 a) output capacitance 1 v oh v oh v ol v ol c out 1, 2, 3 4.5 2.4 -- -- -- -- -- -- -- 5 -- -- 0.4 0.1 -- v v v v pf t able 7. 9240lp s witching c haracteristics 1 (t a = -55 to +125c with avdd = 5v, dvdd = 5v, drvdd = 5v, r bias = 2 k w, c l = 20 p f) 1. guaranteed by design. t iming d iagram p arameter s ymbol m in t yp m ax u nits clock period clock pulse width high clock pulse width low output delay pipeline delay (latency) t c t ch t cl t od 100 45 45 8 -- -- -- -- 13 3 -- -- -- 19 -- ns ns ns ns clock cycles
memory 8 all data sheets are subjec t to change without notice ?2002 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/ d converter with lpt asic 9240lp 03.08.02 rev 4 q44-06 note: all dimensions in inches 44 p in r ad -p ak ? q uad f lat p ackage s ymbol d imension m in n om m ax a 0.185 0.205 0.225 b 0.015 0.017 0.019 c 0.008 0.010 0.012 d 0.643 0.650 0.657 d1 0.500 bsc e 0.050 bsc s1 0.005 0.067 -- l 0.260 0.270 0.280 q 0.020 0.025 0.030 n44 r ecommended e xternal r eference sel c ross s ection
memory 9 all data sheets are subjec t to change without notice ?2002 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/ d converter with lpt asic 9240lp 03.08.02 rev 4 important notice: these data sheets are created using the chip manufacturer ?s published specifications. maxwell technologies verifies functionality by testing key parameters either by 100% testing, sample test ing or characterization. the specifications presented within these data sheets repr esent the latest and most accurate information available to date. however, these specifications are subject to change without notice and maxwell technologies assumes no responsibility for the us e of this information. maxwell technologies? products are not authorized for use as critical components in li fe support devices or systems without express written approval from maxwell technologies. any claim against maxwell technologies must be made within 90 days from the date of shipment from maxwell tech- nologies. maxwell technologies? liability shall be limited to replacement of defective parts.
memory 10 all data sheets are subjec t to change without notice ?2002 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/ d converter with lpt asic 9240lp 03.08.02 rev 4 product ordering options model number feature option details 9240lp rp q x screening flow package radiation feature base product nomenclature monolithic s = maxwell class s b = maxwell class b e = engineering (testing @ +25c ) i = industrial (testing @ -55c, +25c, +125c) q = quad flat pack rp = r ad -p ak ? package 14-bit, 10msps monolithic a/d converter with lpt asic
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